Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.
History

Wed, 02 Jul 2025 14:15:00 +0000

Type Values Removed Values Added
Weaknesses CWE-266
Metrics cvssV3_1

{'score': 9.1, 'vector': 'CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H'}

ssvc

{'options': {'Automatable': 'yes', 'Exploitation': 'none', 'Technical Impact': 'partial'}, 'version': '2.0.3'}


Tue, 01 Jul 2025 20:15:00 +0000

Type Values Removed Values Added
Description Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.
References

cve-icon MITRE

Status: PUBLISHED

Assigner: mitre

Published: 2025-07-01T00:00:00.000Z

Updated: 2025-07-02T13:58:38.672Z

Reserved: 2025-04-22T00:00:00.000Z

Link: CVE-2025-45006

cve-icon Vulnrichment

Updated: 2025-07-02T13:55:40.154Z

cve-icon NVD

Status : Awaiting Analysis

Published: 2025-07-01T20:15:24.993

Modified: 2025-07-03T15:14:12.767

Link: CVE-2025-45006

cve-icon Redhat

No data.