The caching invalidation guidelines from the AMD-Vi specification (48882—Rev
3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction
(see stale DMA mappings) if some fields of the DTE are updated but the IOMMU
TLB is not flushed.
Such stale DMA mappings can point to memory ranges not owned by the guest, thus
allowing access to unindented memory regions.
Metrics
Affected Vendors & Products
References
Link | Providers |
---|---|
https://xenbits.xenproject.org/xsa/advisory-442.html |
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History
Wed, 18 Jun 2025 16:15:00 +0000
Type | Values Removed | Values Added |
---|---|---|
Weaknesses | CWE-672 | |
Metrics |
ssvc
|

Status: PUBLISHED
Assigner: XEN
Published: 2024-01-05T16:30:57.225Z
Updated: 2025-06-18T15:48:27.234Z
Reserved: 2023-06-01T10:44:17.065Z
Link: CVE-2023-34326

Updated: 2024-08-02T16:10:06.955Z

Status : Modified
Published: 2024-01-05T17:15:08.637
Modified: 2025-06-18T16:15:21.167
Link: CVE-2023-34326

No data.