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Total 4 CVE
CVE Vendors Products Updated CVSS v3.1
CVE-2025-10263 1 Arm 20 C1-premium, C1-ultra, Cortex-a710 and 17 more 2026-06-09 9.1 Critical
Arm C1-Ultra, C1-Premium, Neoverse V3 & V3AE, Neoverse V2, Neoverse V1, Neoverse-N2, Neoverse-N1, Cortex-X925, Cortex-X4, Cortex-X3, Cortex-X2, Cortex-X1 & X1C, Cortex-A710, Cortex-A78, A78AE & A78C, Cortex-A77, Cortex-A76 & A76A may allow writes to resources owned by a higher exception level.
CVE-2025-0647 1 Arm 23 C1-premium, C1-premium Firmware, C1-ultra and 20 more 2026-01-26 7.9 High
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
CVE-2024-5660 1 Arm 32 Cortex-a710, Cortex-a710 Firmware, Cortex-a77 and 29 more 2026-01-05 9.8 Critical
Use of Hardware Page Aggregation (HPA) and Stage-1 and/or Stage-2 translation on Cortex-A77, Cortex-A78, Cortex-A78C, Cortex-A78AE, Cortex-A710, Cortex-X1, Cortex-X1C, Cortex-X2, Cortex-X3, Cortex-X4, Cortex-X925, Neoverse V1, Neoverse V2, Neoverse V3, Neoverse V3AE, Neoverse N2 may permit bypass of Stage-2 translation and/or GPT protection.
CVE-2024-7881 1 Arm 18 C1-premium, C1-premium Firmware, C1-pro and 15 more 2025-12-18 5.1 Medium
An unprivileged context can trigger a data memory-dependent prefetch engine to fetch the contents of a privileged location and consume those contents as an address that is also dereferenced.